Dynamic random access memory (DRAM) devices provide the benefits of higher storage densities and less power consumption in comparison to other memory technologies, including and most notably, static random access memory (SRAM) devices. However, these benefits come at the cost of incurring various required delays before and/or after each access for reading, writing and other functions to allow the memory cells and other components within DRAM devices to be prepared for a subsequent access. Examples of such delays are row precharges, refresh operations, row activation, etc. Attempts at efficiently managing these myriad delays has resulted in the creation of commands to allow the times at which these various delays are incurred to be more precisely controlled, but this creates the additional overhead of additional commands needing to be transmitted between reading and writing accesses.
It has also become common practice to attempt to reduce both costs and the physical size of DRAM devices by multiplexing multiple functions onto the various signal input and outputs. However, this multiplexing requires multiple phases to transmit commands and/or addresses, effectively replacing physical separation of signals with temporal separation in which more time is required to allow various signal inputs and outputs to first serve one function and then serve at least a second, if not more functions. One example of multiplexing that brings about such a cost in time arises from the separation of addresses transmitted to DRAM devices into at least two parts (usually at least a row and a column address) that are then multiplexed onto the same input signals such that a first part of the address must be sent during one distinct time period, followed by at least a second part of the address being sent during at least one more distinct time period. This temporal separation into distinct phases increases, yet again, the overhead for the myriad commands required.
As DRAM devices have become progressively faster as a result of advances in the design of both the DRAM cells making up a DRAM device and in the transistors, etc., used to make up the DRAM cells, the speed at which the interfaces made up of the multiplexed input and output signals of DRAM devices operate have needed to increase. In an effort to achieve higher interface speeds while maintaining integrity in the transmission of commands, addresses and data, it has become common practice to synchronize the various phases and functions performed by multiplexed inputs and outputs to a clock signal to ensure that the states of the various inputs and outputs are transmitted and latched at appropriate times. Initially, whole clock cycles were commonly used as the timing basis for events on a memory bus. However, even speedier DRAM devices have resulted in the more recent adoption of half clock cycles as the timing basis for events on a memory bus, resulting in what has been referred to as “double-clocking” of signals, or what is more commonly referred to in reference to common SDRAM (synchronous DRAM) devices as “DDR” or “double data rate” devices. Although the increased speeds of interfaces would seem to provide an opportunity to fully accommodate the overhead of the many required commands, difficulties have been encountered at such higher interface speeds in meeting the more stringent signal setup and hold timing requirements in the transmission of each of the various phases required in the transmission of each of the myriad commands and/or addresses. These difficulties have been such that it has been proposed that commands and/or addresses be transmitted at only up to half the clock rate at which data is transferred in what has been called “2n clocking,” thus denying the benefits of double-clocking to the transmission of commands and/or addresses.
The cumulative time penalties resulting from these various difficulties in transmitting commands and/or addresses have started to become significant to an extent rivaling the time lost to preparing the DRAM cells for being accessed. Indeed, there is growing concern that the overhead required for transferring addresses and/or commands may take up more of the available bandwidth of a memory bus than is required for the actual transferring of data.